pdu1016h doc #97044 data delay devices, inc. 1 12/16/97 3 mt. prospect ave. clifton, nj 07013 4-bit, ecl-interfaced programmable delay line (series pdu1016h) features packages digitally programmable in 16 delay steps monotonic delay-versus-address variation precise and stable delays input & outputs fully 10kh-ecl interfaced & buffered fits 32-pin dip socket functional description the pdu1016h-series device is a 4-bit digitally programmable delay line. the delay, td a , from the input pin (in) to the output pin (out) depends on the address code (a3-a0) according to the following formula: td a = td 0 + t inc * a where a is the address code, t inc is the incremental delay of the device, and td 0 is the inherent delay of the device. the incremental delay is specified by the dash number of the device and can range from 0.5ns through 100ns, inclusively. the enable pin (enb) is held low during normal operation. when this signal is brought high, out is forced into a low state. the address is not latched and must remain asserted during normal operation. series specifications total programmed delay tolerance: 5% or 1ns, whichever is greater inherent delay (td 0 ): 5.5ns typical for dash numbers up to 5, greater for larger #?s setup time and propagation delay: address to input setup (t ais ): 3.6ns disable to output delay (t diso ): 1.7ns typical operating temperature: 0 to 70 c temperature coefficient: 100ppm/ c (excludes td 0 ) supply voltage v ee : -5vdc 5% power dissipation: 615mw typical (no load) minimum pulse width: 20% of total delay 1997 data delay devices data delay devices, inc. 3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 n/c n/c out gnd enb n/c n/c n/c gnd enb n/c in n/c a2 a1 vee a0 n/c n/c n/c vee a3 n/c n/c 32 31 26 25 24 1 2 7 8 9 11 15 16 gnd enb a0 vee gnd in a3 vee gnd out a1 a2 gnd pdu1016h-xxc4 smd pdu1016h-xxmc4 mil smd pdu1016h-xx dip pdu1016h-xxm mil dip pin descriptions in signal input out signal output a0-a3 address bits enb output enable vee -5 volts gnd ground dash number specifications part number incremental delay per step ( ns) total delay ( ns) pdu1016h-.5 0.5 0.3 7.5 1.0 pdu1016h-1 1.0 0.5 15 1.0 pdu1016h-2 2.0 0.5 30 1.5 pdu1016h-3 3.0 1.0 45 2.2 pdu1016h-4 4.0 1.0 60 3.0 pdu1016h-5 5.0 1.0 75 3.7 pdu1016h-6 6.0 1.0 90 4.5 pdu1016h-8 8.0 1.0 120 6.0 pdu1016h-10 10.0 1.5 150 7.5 pdu1016h-15 15.0 1.5 225 11.2 pdu1016h-20 20.0 2.0 300 15.0 pdu1016h-25 25.0 2.5 375 18.8 pdu1016h-30 30.0 3.0 450 22.5 pdu1016h-40 40.0 4.0 600 30.0 pdu1016h-50 50.0 5.0 750 37.5 pdu1016h-60 60.0 6.0 900 45.0 pdu1016h-80 80.0 8.0 1200 60.0 pdu1016h-100 100.0 10.0 1500 75.0 note: any dash number between .5 and 100 not shown is also available.
pdu1016h doc #97044 data delay devices, inc. 2 12/16/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes address update the pdu1016h is a memory device. as such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. the timing restrictions are shown in figure 1. after the last signal edge to be delayed has appeared on the out pin, a minimum time, t oax , is required before the address lines can change. this time is given by the following relation: t oax = max { (a i - a i-1 ) * t inc , 0 } where a i-1 and a i are the old and new address codes, respectively. violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t oax has elapsed. a similar situation occurs when using the enb signal to disable the output while in is active. in this case, the unit must be held in the disabled state until the device is able to ?clear? itself. this is achieved by holding the enb signal high and the in signal low for a time given by: t dish = a i * t inc violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t dish has elapsed. input restrictions there are three types of restrictions on input pulse width and period listed in the ac characteristics table. the recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. the suggested conditions are those for which signals will propagate through the unit without significant distortion. the absolute conditions are those for which the unit will produce some type of output for a given input. when operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. however, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. in other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. please consult the technical staff at data delay devices if your application has specific high-frequency requirements. please note that the increment tolerances listed represent a design goal. although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. monotonicity is, however, guaranteed over all addresses. t diso t oax t aens t enis pw in td a pw out t dish a3-a0 enb in out figure 1: timing diagram a i-1 a i t ais
pdu1016h doc #97044 data delay devices, inc. 3 12/16/97 3 mt. prospect ave. clifton, nj 07013 device specifications table 1: ac characteristics parameter symbol min typ units total programmable delay td t 15 t inc inherent delay td 0 5.5 ns* disable to output low delay t diso 1.7 ns address to enable setup time t aens 1.0 ns address to input setup time t ais 3.6 ns enable to input setup time t enis 3.6 ns output to address change t oax see text disable hold time t dish see text absolute per in 16 % of td t input period suggested per in 40 % of td t recommended per in 200 % of td t absolute pw in 8 % of td t input pulse width suggested pw in 20 % of td t recommended pw in 100 % of td t * greater for dash numbers larger than 5 table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v ee -7.0 0.3 v input pin voltage v in v ee - 0.3 0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 75c) parameter symbol min typ max units notes high level output voltage v oh -1.020 -0.735 v v ih = max,50 w to -2v low level output voltage v ol -1.950 -1.600 v v il = min, 50 w to -2v high level input voltage v ih -1.070 v low level input voltage v il -1.480 v high level input current i ih 475 m a v ih = max low level input current i il 0.5 m a v il = min
pdu1016h doc #97044 data delay devices, inc. 4 12/16/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com package dimensions pdu1016h-xx (commercial dip) pdu1016h-xxm (military dip) .150 .030 1.650 typ. 1 2 7 8 16 15 11 9 .320 max. .018 typ. .400 typ. .300 typ. .012 typ. .020 typ. 31 32 25 26 24 .100 .600 .700 .800 1.000 1.400 1.500 .075 pdu1016h-xxc4 (commercial smd) pdu1016h-xxmc4 (military smd) 1.280 .020 .882 .005 .020 typ. .040 typ. .100 .090 1.100 .280 max. .590 max. .010 .002 .050 .010 .710 .005 .007 .005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
pdu1016h doc #97044 data delay devices, inc. 5 12/16/97 3 mt. prospect ave. clifton, nj 07013 delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 50 w to -2v supply voltage ( vcc): -5.0v 0.1v c load : 5pf 10% input pulse: standard 10kh ecl threshold: (v oh + v ol ) / 2 levels (rising & falling) source impedance: 50 w max. rise/fall time: 2.0 ns max. (measured between 20% and 80%) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for te st only and do not in any way restrict the operation of the device. out out trig in ref trig test setup device under test (dut) oscilloscope pulse generator in address select timing diagram for testing t rise t fall per in pw in t rise t fall 20% 20% 50% 50% 80% 80% 50% 50% v ih v il v oh v ol input signal output signal
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